The drive for faster, more reliable, and more compact computer components has led to extensive use of electrical interconnects such as solder ball connectors. Solder ball interconnects are a commonly employed device for connecting semiconductor dice to the leads of a package, or other components. This approach is exemplified by modern flip chip designs, where a die itself is used as a package, and solder balls on the die are used to attach the package to a printed circuit board. For more information on flip chips, see National Semiconductor's MicroSMD package datasheets, which are incorporated herein by reference. When used in this manner, solder ball connectors can offer significant advantages. For example, solder balls produce low parasitic inductance in relation to the longer bond wires typically used with more traditional packages, thus making them more suitable for some high-speed applications. Flip chips with solder balls also take up significantly less space than other types of packages, allowing for devices with much smaller footprints.
Even though these solder ball interconnects provide flip chip packages many advantages, such interconnects are not without their disadvantages. Solder balls are subjected to stresses during various semiconductor fabrication operations, and often transmit these stresses to the delicate circuitry of semiconductor dies. For example, solder balls are often compressed during various fabrication processes, such as when flip chip solder balls are pressed against the printed circuit board during attachment. Such compressive forces can crush the underlying circuitry of the die.
To alleviate this problem, conductive bump pads are often placed underneath the solder balls to spread any stresses out over a wider area and protect any underlying circuits. However, such bump pads can generate a parasitic capacitance when placed too close to active circuitry, thus hindering performance of the circuits. To further explain this problem, FIG. 1A illustrates a cutaway side view of a solder bump interconnect constructed in accordance with the prior art. Ordinarily, a semiconductor substrate 300 has a number of interconnects 200 formed on it, to allow for electrical connection to other devices. The interconnect has a circularly shaped, or disclike, bump pad 210 (a top view of which is illustrated in FIG. 1B) followed by a passivation layer 220, a benzocyclobutene (BCB) layer 230, a layer of under bump metal (UBM) 240 for better solder adherence, and a solder ball 250.
When the solder ball 250 is subjected to forces, such as when it is compressed during attachment to a printed circuit board, these forces generate stresses in the circuitry within the substrate 300. Accordingly, rigid bump pads 210 are placed underneath the solder ball 250 to distribute stresses over a larger area. One can easily see that, absent the bump pad 210, stresses would be roughly concentrated in the area of the passivation opening 260, whereas the bump pad 210 instead acts to distribute stresses generally over the entire area associated with its outer radius 270. However, the large bump pad 210 is also electrically conductive, and acts to electrically connect the solder ball 250 to other circuitry within the substrate 300. Consequently, the bump pad 210 interacts with underlying circuitry to produce a parasitic capacitance. Indeed, such parasitic capacitances are common in situations such as these, where an electrically active bump pad 210 and electrically active circuits within the substrate 300 are placed close together yet separated by a dielectric (here, the dielectric or passivation material deposited between the circuits and the bump pad 210 to insulate them from each other), allowing a capacitative charge to build. Specifically, the size of the bump pad 210 means that any circuitry within the substrate 300 and underneath the bump pad 210 can contribute to parasitic capacitance, reducing chip performance, especially in the multi-GHz range.
It would therefore be desirable to develop an electrical interconnect capable of supporting a solder bump and alleviating any of its associated stresses, while generating minimal parasitic capacitance.